Implementation of Parallel Binary Adder

A Parallel Binary Adder is a combinational circuit that performs that adds two bits and a carry and outputs a sum bit and a crry bit. When we want to add two binary numbers ,each having two or more bits,the LSBs can be added by using a half adder. The carry resulted from the addition of the LSBs is carried over to the next significant column and added to the two bits in that column. So, in the second and higher columns, the two data bits of that column and the carry bit generated from the addition in the previous column need to be added.The full adder adds the bits A and B and the carry from the previous column called the carry in (Cin) and the outputs the sum bit (S) and the carry bit called the carry out (Cout). The variable S gives the value of the least significant bit of the sum. The variable Cout gives the outout carry.