Flip-flops are synchronous bistable devices, also known as bistable multivibrators. Here synchronous means that the output changes state only at a specific point on a triggering input called the clock (CLK), which is designated as a control input C; that is, changes in the output occur in synchronization with the clock. An edge-triggered flip-flop changes state either at the positive edge (riging edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock.

Edge-Triggered J-K Flip-Flop

The J-K flip-flop is versatile and is a widely used type of flip-flop. The J and K designations for the inputs have no known significance except that they are adjucent letters in the alphabet.The function of J-K flip-flop is identical to that of the S-R flip-flop in the SET, RESET and no-change conditions of operation. The difference is that the J-K flip-flop has no invalid state as does the S-R flip-flop. The input mark J is for set and the input mark K is for reset. When both inputs J and K are equal to 1, the flip flop switches to its complement state, that is, if Q = 1, it switches to Q = 0 and vice versa. A J-K flip-flop constructed with two crossed coupled NOR gates and two AND gates. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similerly output Q' is ANDed with J and CP inputs so that the flip is set with a clock pulse only when Q' was previously 1. When both J and K are 1, the input pulse is transmitted through one AND gate only; the one whose input is connected to the flip-flop output that is presently equal to 1 . Thus if Q = 1, the output of the upper AND gate becomes 1 upon application of the clock pulse and the flip-flop is cleared. If Q' = 1, the output of the lower of the lower AND gae becomes 1 and the flip-flop is set. In either case the output of the flip-flop is complemented. It is very important to realize that because of the feedback connection in the JK flip-flop, a CP pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing untill the pulse goes back to 0. To avoid this udesirable operation, the clock pulse must have a time duration that is shorter than the propegation delay time of the flip-flop.